1. Field of Invention
The invention relates to a pixel array substrate and a display panel, and more particularly to a pixel array substrate and a display panel having a dual trace.
2. Description of Related Art
With the vigorous development of display technologies, display panels have been applied in display devices of various dimensions, such as televisions, computer monitors, notebook computers, mobile phones, etc. Taking televisions for example, the consumer not only has demands in display properties such as resolution, contrast, and viewing angle, but the consumer is also increasingly making exterior aesthetics a deciding factor for purchase. Therefore, in order to satisfy consumer demands, manufacturers of display panels have devoted resources into developing slim border display panels, in which display panels having a same display quality achieve properties of lightness, thinness, slimness, and compactness.
In order to achieve display panels with slim borders, panel manufacturers need to reduce a distributed area of peripheral traces so as to reduce the width of the border. In conventional techniques, sophisticated lithography processes are employed to reduce the spacing between peripheral traces, thereby achieving the slim border display panel. However, as high-end televisions developed and the resolution of display panels has become more and more enhanced, the quantity of peripheral traces has also increased, which has caused difficulties in reducing the width of the display panel border.
Among the conventional techniques of reducing the border, a dual trace technique has been proposed. In this technique, since two neighboring peripheral traces belong to different layers, the distance between two peripheral traces can be shorter than two peripheral traces belonging to a same layer. Accordingly, the border width of the display panel is reduced. Nevertheless, in conventional dual trace techniques, the traces disposed in one of the layers need be jumped through conductive patterns to connect with the signal lines in the display region, whereas the traces in another layer belong to the same layer as the signal lines in the display region, and therefore these traces do not require conductive patterns to connect to the signal lines. Accordingly, the resistance values between the traces and the signal lines in one of the layers are clearly different from the resistance values between the traces and the signal lines in the other layer. Therefore, the display panels adopting this design would likely have an issue with bright and dark lines.